library ieee;
use ieee.std_logic_1164.all;

entity aludec is
port (  func		: in std_logic_vector(5 downto 0);
		aluop		: in std_logic_vector(1 downto 0);
        alucontrol	: out std_logic_vector(2 downto 0));
end entity;

architecture arch of aludec is
begin
    process (func, aluop)
    begin
        if (aluop = "00") then
       		alucontrol <= "010";
        elsif (aluop = "01") then
        	alucontrol <= "110";
        else
		    if (func = "100000") then
		    	alucontrol <= "010";
		    elsif (func = "100010") then
		   		alucontrol <= "110";
		    elsif (func = "100100") then
		   		alucontrol <= "000";
		    elsif (func = "100101") then
		    	alucontrol <= "001";
		    elsif (func = "101010") then
		    	alucontrol <= "111";
		    end if;
	   	end if;
    end process;
end architecture;
